Electronic device configured as a multichip module, leadframe and panel with leadframe positions

ABSTRACT

An electronic device has, as a multichip module, two or more semiconductor chips that are integrated into a leadframe such that a placement side of the leadframe and the active top sides of the circuit chips are flush and have a common fine wiring plane. The leadframe is arranged as an expanded semiconductor chip on a rewiring substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a divisional application of application Ser. No. 10/696,369,filed Oct. 29, 2003; the application also claims the priority, under 35U.S.C. §119, of German patent application No. 102 50 538.1, filed Oct.29, 2002; the prior applications are herewith incorporated by referencein their entirety.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to an electronic device configured as a multichipmodule, a leadframe arranged in the electronic device and a panel havinga plurality of leadframe positions.

An obstacle to the increasing miniaturization of integrated circuits isthe required dimensions of passive components, such as coils andcapacitors, since they take up a comparatively large semiconductor chiparea. Moreover, design variants and degrees of freedom of design areconsiderably restricted by the requirement of arranging contact areaseither in the edge regions or in a respective central region of thechips. When a plurality of semiconductor chips are combined to form amodule assembly, the chip design is extremely complex because of therequirement. If two semiconductor chips are intended to be wiredtogether, then it ranges from difficult to impossible to coordinatetheir chip designs exactly with one another, especially if thesemiconductor chips originate from different suppliers. Furthermore, itis often necessary to provide a plurality of contact areas for thesupply of semiconductor chips, which necessitates additionalsemiconductor chip area. These disadvantages are also not overcome bythe method for producing the multichip module disclosed in U.S. Pat. No.5,556,812.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide an electronicdevice configured as a multichip module, a leadframe arranged in theelectronic device and a panel having a plurality of leadframe positions,which overcome the above-mentioned disadvantages of the prior artapparatus and methods of this general type.

In particular, it is an object of the invention to provide an electronicdevice that permits more extensive miniaturization of the active topside of semiconductor chips.

With the foregoing and other objects in view there is provided, inaccordance with the invention, an electronic device having two or moresemiconductor chips with contact areas on their active top sides. Thesesemiconductor chips are integrated into a leadframe in such a way that aplacement side of the leadframe and the active top sides of thesemiconductor chips are flush and have a common fine wiring plane. Thisfine wiring plane has interconnects that are so fine that it is possibleto reduce the area requirement of the contact areas on the active topside of the semiconductor chip. Furthermore, the common fine wiringplane enables area-intensive passive components such as coils,capacitors, comb filters and other area-intensive components to be movedfrom the active top side of the semiconductor chip into the common finewiring plane.

In the edge region of the leadframe, the fine wiring plane has contactpads that are connected via bonding connections to bonding areas of arewiring substrate carrying the leadframe. For this purpose, therewiring substrate has an edge region that is not covered by theleadframe. Bonding areas of the rewiring substrate are arranged on theedge region.

Since the contact areas of the semiconductor chips are connected tointerconnects only in the fine wiring plane and have no areas forarea-intensive bonding connections, these contact areas may be madesignificantly smaller than the contact pads on the leadframe and alsosmaller than the bonding areas on the rewiring substrate. Consequently,not only is it possible to reduce the size of the contact areas of thesemiconductor chips, but they also no longer need be limited to the edgeregion and/or to a central bonding channel on the active top side of asemiconductor chip. Rather, it is now possible to accord the designdevelopment greater freedoms for arranging the contact areas.Consequently, the entire surface of the semiconductor chip is availablefor an arbitrary arrangement of miniaturized contact areas.

Arranged on the rewiring substrate is a housing, into which are packagedthe components on the rewiring substrate, such as is bonding wires, aleadframe with a fine wiring plane and embedded semiconductor chips. Theunderside of the rewiring substrate simultaneously forms an outer sideof the electronic device and has external contacts of the electronicdevice which are distributed on the underside.

The semiconductor chips may have different sizes with regard to theirthickness and their active surfaces, and also can have differentintegrated circuits. The differences in thickness can be leveled out bythe leadframe material. Only the active top sides of the semiconductorchips have to be adapted in flush fashion to the top side of theleadframe in order to provide a prerequisite for a common fine wiringplane.

The common fine wiring plane may have electrical interconnects betweenthe contact areas of the two or more semiconductor chips. Thesemiconductor chips can thus be wired together with one another via thefine wiring plane.

Furthermore, the common fine wiring plane may have electricalinterconnects between the contact areas of the semiconductor chips andthe contact pads in the edge region of the leadframe. In this case, itis not important that the contact areas of the semiconductor chips arearranged only in the edge region or in a central bonding region of thesemiconductor chips, rather they can be distributed arbitrarily on thesurface of the semiconductor chip and are nevertheless connected via thefine wiring plane to area-intensive bonding connections via the contactpads of the leadframe.

The fine wiring plane may have thin-film conductors, which aredistinguished by their small thickness of a few hundred nanometers andtheir small width, which may likewise lie in the submicron range. It isthus possible to provide only contact areas of correspondinglyminiaturized external dimensions on the semiconductor chips as well.

Furthermore, the fine wiring plane may be populated with passivediscrete electronic components. Discrete components of this type mayhave resistors, capacitors or coils. The electrodes of which may beconnected via the fine wiring plane to electrodes of the components ofthe integrated circuit of the semiconductor chips. In particular, it ispossible to apply coils to the placement side of the leadframe, whichnot only cover the semiconductor chip, but are larger than the activetop side of the semiconductor chip. Coils of this type mayadvantageously be arranged approximately half on the semiconductor chipand approximately half on the leadframe.

Furthermore, the fine wiring plane may have thin-film components, inparticular electrical resistors, comb filters, inductive componentsand/or capacitive components. Components of this type may be realizeddirectly with the fine wiring in the fine wiring plane. For thispurpose, electrical resistors have fine wiring interconnects arranged ina meandering form, while inductive components have fine wiringinterconnects arranged in a spiral form or a cochleate form. This hasthe advantage that it is possible to reduce the number of placementdevices on the leadframe. Furthermore, it is possible to achieve largerresistances or larger inductances or capacitances than are possible onthe active top sides of the semiconductor chips.

The rewiring substrate not only carries the leadframe on its top sideand the external contacts of the electronic device on its underside, buthas next to the bonding areas, rewiring lines and through contacts whichconnect the bonding areas to external contact areas. External contactsof the electronic device may be arranged on the external contact areas.

Despite the leadframe, an additional rewiring substrate for thiselectronic device is provided so that coarse wiring planes, that is tosay rewiring lines with cross sections that correspond to the crosssection of the bonding wires, are made available. The cross section ofthe lines differs from the fine wiring structure by about one order ofmagnitude.

The invention furthermore relates to a panel having a plurality ofleadframe positions. Each leadframe position has a leadframe for theelectronic device. The leadframe positions in the panel are arranged inrows and columns. The panel corresponds in form and size to asemiconductor wafer. This has the advantage that fine wiring structureslike those that are possible when producing semiconductor chips onsemiconductor wafers can also be employed for the common fine wiringplane. In this case, on the panel, not just one leadframe, but aplurality of leadframes are simultaneously provided with fine wiringstructures. A panel of this type including leadframe positions cansubsequently advantageously be separated into individual leadframes forelectronic devices.

A method for producing an electronic device, which has a plurality ofsemiconductor chips that are embedded in a common leadframe, works withtwo different panels. First, a first panel, which has a plurality ofleaframe positions, and a second panel, which has a plurality of devicepositions, is arranged on a rewiring plate with a plurality of rewiringsubstrates.

First of all, in the context of the production of an electronic device,a first panel is produced with leadframe positions arranged in rows andcolumns. In this case, in each leadframe position of the first panel,two or more semiconductor chips are embedded in the material of theleadframe in such a way that the active top sides of the semiconductorchips become flush with one of the two top sides of the first panel.Afterward, on this panel, a common fine wiring structure is applied tothe active top sides of the semiconductor chips and to the top side ofthe first panel in each leadframe position. Corresponding contact padsare in the edge regions of each leadframe position. The top sides of thesemiconductor chips are flush with the top side of the first panel. Thisfirst panel is then separated into individual leadframes.

Temporally independently of the production of a first panel, a rewiringplate with device positions arranged in rows and columns is produced asthe baseplate of a second panel. In this case, bonding areas arearranged in edge regions of each device position, which are connectedvia rewiring lines and through contacts to external contact areas on therewiring plate in each of the device positions. The leadframes separatedfrom the first panel can then be applied to the rewiring plate in eachof the device positions of the rewiring plate whilst leaving free theedge regions with bonding areas. Afterward, bonding connections arecarried out between the contact pads of the leadframe and the bondingareas of the rewiring plate in each device position.

Finally, a second panel is produced by covering the device positionswith a plastic housing composition. Before the panel is separated intoindividual electronic devices, external contacts may be provided oncontact areas of the underside of the rewiring plate. However, theapplication of external contacts may additionally be effected for eachdevice individually after the panel has been separated into individualelectronic devices.

This method has the advantage that the individual method steps forproducing an electronic device can be effected simultaneously and inparallel for a plurality of devices by producing a first and a secondpanel. Furthermore, the first panel may be embodied in wafer form, withthe result that it is possible to carry out all the technologies forpatterning a fine wiring structure by using installations, apparatus andmethods that are known from silicon planar technology.

For applying a common fine wiring structure, it is possible to use aphotolithography method for the fine patterning of metal closed or solidlayers applied extensively and uniformly over the respective area.Photolithography methods of this type have already been developed tosuch an extent that submicron structures are possible for theinterconnects in the common fine wiring structure.

As an alternative, for applying a fine wiring structure to the firstpanel or a rewiring structure to the rewiring plate, a conductive pastemay be printed on and subsequently sintered to form interconnects,contact pads, bonding areas and/or passive components. A method of thistype has the advantage that an unpatterned application of closed metallayers is obviated, especially since the conductive paste can be printedon in its end structure onto the leadframe or onto the rewiring plate,respectively. If the material of the contact areas that are printed onor produced by photolithography cannot directly be connected to bondingwires, then the contact areas are coated with a bondable material. On amaterial of this type, the bonding connections may then be produced bythe thermocompression bonding of bonding wires on the contact pads.

The embedding of the leadframe with the bonding connections on therewiring plate may also be effected before dividing the rewiring plateinto individual electronic devices by using a transfer molding method,thereby producing a second panel having device positions arranged inrows and columns, which are subsequently separated out from the panel.

To summarize, it should be emphasized that the present inventionrealizes a leadframe with integrated semiconductor chips that can beprocessed further by using thin-film processes or processes comparablewith those from wafer production in order to produce a fine wiring. Thisfine wiring enables very exact and small structures that permitconnections between two chips on a confined area. The patterning makesit possible to produce installation locations and placement locationsfor passive components on the entire leadframe area. The fine wiring onthe carrier makes it possible, finally, to route the power supplydirectly to the semiconductor chip. Furthermore, it is possible toreduce the housing thickness for the later components on the finished,patterned, and populated leadframe by using a grinding-back process. Viathe fine wiring on the leadframe with integrated semiconductor chips,the signals are passed to the outer edge to contact pads.

After the finished patterned and populated leadframe has been mountedonto a rewiring substrate, the contact connection can be effected bywire bonding technology. In this case, all of the bonding wires areshort and are situated at the edge of the leadframe. This edge positionensures that a housing can also have a high number of connections. Theuse of the fine wiring plane ensures that the contact pads of theleadframe are distributed uniformly between four edge side regions. Theuse of a leadframe with integrated semiconductor chips produces, inprinciple, a new chip that can be optimized with regard to therequirements of a housing.

Other features which are considered as characteristic for the inventionare set forth in the appended claims.

Although the invention is illustrated and described herein as embodiedin an electronic device configured as a multichip module, a leadframearranged in the electronic device and a panel having a plurality ofleadframe positions, it is nevertheless not intended to be limited tothe details shown, since various modifications and structural changesmay be made therein without departing from the spirit of the inventionand within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic cross sectional view through a leadframeposition of a first panel;

FIG. 2 is a diagrammatic cross sectional view as shown in FIG. 1, butwith a fine wiring structure in the leadframe position;

FIG. 3 is a diagrammatic cross sectional view as shown in FIG. 2, butwith a discrete passive component on the fine wiring structure;

FIG. 4 is a plan view of a device position of a second panel prior tobeing packaged in a plastic housing composition; and

FIG. 5 is a cross sectional view of an electronic device taken along thesection line A-A in FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1 thereof, there is shown a diagrammatic crosssectional view through a leadframe position 23 of a first panel. Thisfirst panel essentially has a plurality of leadframe positions arrangedin rows and columns. This first panel essentially corresponds in formand size to a semiconductor wafer. However, the material of this waferis not a semiconductor plate, but rather a plastic plate, in which case,in each of the leadframe positions 23, as shown in FIG. 1, semiconductorchips 2 are integrated in such a way that the active top sides 5 of thesemiconductor chips 2 terminate flush with the placement side 8 of theleadframe 7. The thickness d of the semiconductor chips 2 lies in therange of between 50 μm and 750 μm and may vary from semiconductor chipto semiconductor chip in a respective leadframe position. The thicknessD of the plastic material 24 is adapted to the thickness d of thethickest of the semiconductor chips 2 within a leadframe position, sothat the passive rear side 31 of the semiconductor chip 2 is covered byplastic material.

In this embodiment of FIG. 1, after the semiconductor chips 2 had beenintroduced into the plastic material 24, the first panel was subjectedto a grinding-back process and ground down to the thickness D.

Contact areas 4 are arranged on the active top side 5 of thesemiconductor chips 2. The extent of the contact areas 4 is representedto be significantly larger than the true extent of contact areas 4 ofthis type. It is actually smaller than contact areas on semiconductorchips that have to receive bonding wires. Consequently, the dimensionsof these contact areas 4 of the semiconductor chips 2 lie in a rangethat is smaller than the diameter of bonding wires.

In this embodiment, the contact area 33 is arranged in the edge regionof the active top side of the semiconductor chip 2, and the contact area34 lies at an arbitrary position between the edge region and the centralregion of the semiconductor chip 2. Such a freely selectable arrangementof the contact area 34, which depends only on the design of theintegrated circuit on the active top side 5 of the semiconductor chip 2,can be selected arbitrarily by the layout designer when designing theinventive electronic device.

The surface for realizing passive component structures and large-areacontact pads for bonding connections is not limited to the surfaceregion of the semiconductor chip 2 in this leadframe position, so thatsuch area-intensive components of an electronic device are realized on acommon fine wiring plane. Components with functions identical to thosein FIG. 1 are identified using the same reference symbols in FIGS. 2 to5 and are not discussed separately.

FIG. 2 shows a diagrammatic cross sectional view as shown in FIG. 1, butwith a fine wiring structure 26 in the leadframe position 23. The finewiring structure 26 is embodied using thin-film technology and thereforehas a thickness δ of between 0.5 and 2.5 μm. The width b of theinterconnects 20 and 21 is of the same order of magnitude as thethickness of the fine wiring structure 26. Consequently, contact areas 4of the same minimal order of magnitude down to the submicron range asfor the width b of the interconnects 20 and 21 are possible for thesemiconductor chip 2.

Contact pads 11 for corresponding bonding connections are arranged onthe edge region in each leadframe position 23. These area-intensivecontact pads 11 thus only take up areas which are available on theplacement side 8 in each of the leadframe positions 23. While theinterconnect 21 connects the contact area 33 of the semiconductor chip 2to a contact pad 11 in the edge region 10 of the leadframe position,interconnects 20 which directly connect contact areas 4 of thesemiconductor chip 2 to contact areas of adjacent semiconductor chipsare also provided on the semiconductor chip 2.

FIG. 3 is a diagrammatic cross sectional view as in FIG. 2, but with adiscrete passive component 22 on the fine wiring structure 26. In thisembodiment, the discrete component 22 is a capacitor. Capacitors cannotbe directly formed by interconnects 20 or 21 like other passivecomponents can be. Other passive components, such as, for example,resistors can be patterned by an arrangement of finely patternedinterconnects in a meandering form, and coils can be patterned by anarrangement of the interconnects 20 and 21 in a spiral form on the finewiring plane. In order to electrically connect a discrete component 22in the fine wiring plane 9 within a leadframe position 23, theinterconnect 35 leading from the contact area 34 to the contact pad 11is interrupted and is bridged by the passive component 22 at theinterruption location. For this purpose, the electrodes 36 of thepassive component 22 are connected to ends of the interconnect 35 at theinterruption location.

After the conclusion of the population of the first panel in each of theleadframe positions of the fine wiring plane 9 with passive components22, the first panel is separated into individual leadframes of eachleadframe position 23 and practically represents an enlarged chip thatcan be applied to a rewiring substrate.

FIG. 4 shows a plan view of a device position 30 of a second panel priorto packaging in a plastic housing composition. This device position 30of the second panel has a rewiring substrate 12, which is part of acontiguous rewiring plate 27 with a plurality of device positions 30.The device positions are arranged in rows and columns in the rewiringplate. The rewiring substrate 12 carries a leadframe 7 separated fromthe first panel. The size of the leadframe 7 is smaller than therewiring substrate 12. Consequently, an edge region 14 having bondingareas 15 remains free on the rewiring substrate 12. The bonding areas 15are connected via bonding wires 29 to contact pads 11 on the leadframe7. Rewiring lines (not shown here) proceed from the bonding areas 15 andlead, via through contacts, to the underside 19 (See FIG. 5) of therewiring substrate 12.

The leadframe 7 shown in FIG. 4 has two semiconductor chips 2 and 3 ofdifferent sizes. The contact areas 4 of these semiconductor chips 2 and3 are partly arranged in edge regions and partly distributed on the topsides 5 and 6 of the semiconductor chips 2 and 3. The fine wiringstructure 26 has interconnects 20 which directly connect contact areas 4of the semiconductor chip 2 to contact areas 4 of the semiconductor chip3. Other interconnects 21 of the fine wiring structure 26 connectcontact areas 4 to contact pads 11 in the edge region 10 of theleadframe 7. Further interconnects 35 of the fine wiring structure 26connect contact areas 4 to contact pads 11 via a passive component 22.

This plan view shows that all of the area-intensive components do nottake up additional active chip surface, but rather are arranged on theplacement side 8 of the leadframe 7. From left to right in FIG. 4, thesection line A-A runs first through the material in the edge region 14of the rewiring substrate 12 and cuts through a bonding area 15 and abonding wire 29 applied on a contact pad 11 of the leadframe 7 by usinga thermocompression pad. From there, the section line A-A continues viathe interconnect 35 through the passive component 22 to a contact area 4that is not arranged at the edge of the semiconductor chip 2.

The section line A-A then cuts through an interconnect 20 which leadsfrom a contact area 4 of the semiconductor chip 2 to a contact area 4 ofthe semiconductor chip 3. Finally, the section line A-A cuts through acontact area 4 in the edge region of the semiconductor chip 2 of theconnected interconnect 21 which leads to a contact pad 11 in the edgeregion 10 of the leadframe 7. On the right-hand side of the deviceposition 30, the section line A-A again cuts through a bonding wirewhich leads to the bonding area 15 in the edge region 14 of the rewiringsubstrate 12.

FIG. 5 shows a diagrammatic cross sectional view of an electronic device1 taken along the section line A-A of FIG. 4. FIG. 5 shows, comparedwith FIG. 4, that the rewiring substrate 12 is covered with a plastichousing composition 28, in which the components carried by the rewiringplate 12 are embedded. Furthermore, FIG. 5 shows external contacts 18arranged in a manner distributed uniformly on the underside 19 of therewiring substrate 12. These external contacts 18 are electricallyconnected to the bonding areas 15 on the top side 13 of the rewiringsubstrate 12 via external contact areas, passage contacts and rewiringlines (not shown). Consequently, in this embodiment of the invention,the contact pads 11 in the edge region 10 of the leadframe 7 areelectrically connected to the external contacts 18 distributed on theunderside 19 and thus on the underside of the electronic device 1.

1. An electronic device, comprising: at least two semiconductor chips,each one of said semiconductor chips having an active top side with aplurality of contact areas; a leadframe having a placement side and anedge region, said semiconductor chips integrated into said leadframesuch that said placement side of said leadframe and said active top sideof each one of said semiconductor chips are flush, said placement sideof said leadframe and said active top side of each one of saidsemiconductor chips having a common fine wiring plane, said fine wiringplane having a plurality of contact pads configured in said edge regionof said leadframe; a rewiring substrate having a top side carrying saidleadframe, said top side of said rewiring substrate having an edgeregion with a plurality of bonding areas, said rewiring substrate havingan underside, said leadframe not covering said edge region of saidrewiring substrate; a plurality of bonding connections configuredbetween said plurality of contact pads of said fine wiring plane of saidleadframe and said plurality of bonding areas of said rewiringsubstrate; a housing packaging said leadframe and said semiconductorchips; and a plurality of external contacts distributed on saidunderside of said rewiring substrate.
 2. The electronic device accordingto claim 1, wherein: said semiconductor chips include a firstsemiconductor chip and a second semiconductor chip; said firstsemiconductor chip has a thickness and said second semiconductor chiphas a thickness that is different from said thickness of said firstsemiconductor chip; said active top side of said first semiconductorchip has size and said active top side of said second semiconductor chiphas size that is different from said size of said active top side ofsaid first semiconductor chip; and said first semiconductor chip has anintegrated circuit and said second semiconductor chip has an integratedcircuit that is different from said integrated circuit of said firstsemiconductor chip.
 3. The electronic device according to claim 1,wherein: each one of said semiconductor chips has a central bondingchannel and a side edge with a plurality of outside contact areas; saidactive top side of each one of said semiconductor chips has a pluralityof arbitrarily distributed additional contact areas located outside saidcentral bonding channel and outside said side edge.
 4. The electronicdevice according to claim 1, wherein: said fine wiring plane has aplurality of electrical interconnects configured between said pluralityof contact areas of one of said semiconductor chips and said pluralityof contact areas of another one of said semiconductor chips.
 5. Theelectronic device according to claim 1, wherein: said fine wiring planehas a plurality of electrical interconnects configured between saidplurality of contact areas and said plurality of contact pads.
 6. Theelectronic device according to claim 1, wherein: said fine wiring planehas a plurality of thin-film interconnects.
 7. The electronic deviceaccording to claim 1, wherein: said fine wiring plane is configured witha plurality of passive discrete electronic components.
 8. The electronicdevice according to claim 1, wherein: said fine wiring plane has aplurality of thin-film components that are each selected from a groupconsisting of an electrical resistor, a comb filter, an inductivecomponent and a capacitive component.
 9. The electronic device accordingto claim 1, wherein: said fine wiring plane has a plurality ofelectrical resistors with a meandering form.
 10. The electronic deviceaccording to claim 1, wherein: said fine wiring plane has a plurality ofinductive components with a spiral form.
 11. The electronic deviceaccording to claim 1, wherein: said rewiring substrate has a pluralityof rewiring lines and a plurality of passage contacts connected to saidplurality of external contacts.
 12. A leadframe configuration,comprising: at least two semiconductor chips, each one of saidsemiconductor chips having an active top side with a plurality ofcontact areas; and a leadframe having a placement side and an edgeregion; said semiconductor chips integrated into said leadframe suchthat said placement side of said leadframe and said active top side ofeach one of said semiconductor chips are flush, said placement side ofsaid leadframe and said active top side of each one of saidsemiconductor chips having a common fine wiring plane, said fine wiringplane having a plurality of contact pads configured in said edge regionof said leadframe.
 13. The leadframe configuration according to claim12, wherein: said fine wiring plane has a plurality of electricalinterconnects configured between said plurality of contact areas of oneof said semiconductor chips and said plurality of contact areas ofanother one of said semiconductor chips.
 14. The leadframe configurationaccording to claim 12, wherein: said fine wiring plane has a pluralityof electrical interconnects configured between said plurality of contactareas and said plurality of contact pads.
 15. The leadframeconfiguration according to claim 12, wherein: said fine wiring plane hasa plurality of thin-film interconnects.
 16. The leadframe configurationaccording to claim 12, wherein: said fine wiring plane is configuredwith a plurality of passive discrete electronic components.
 17. Theleadframe configuration according to claim 12, wherein: said fine wiringplane has a plurality of thin-film components that are each selectedfrom a group consisting of an electrical resistor, a comb filter, aninductive component and a capacitive component.
 18. The leadframeconfiguration according to claim 12, wherein: said fine wiring plane hasa plurality of electrical resistors with a meandering form.
 19. Theleadframe configuration according to claim 12, wherein: said fine wiringplane has a plurality of inductive components with a spiral form.
 20. Apanel, comprising: a plurality of leadframe positions; each one of saidplurality of leadframe positions having a leadframe configurationincluding: at least two semiconductor chips, each one of saidsemiconductor chips having an active top side with a plurality ofcontact areas; and a leadframe having a placement side and an edgeregion; said semiconductor chips integrated into said leadframe suchthat said placement side of said leadframe and said active top side ofeach one of said semiconductor chips are flush, said placement side ofsaid leadframe and said active top side of each one of saidsemiconductor chips having a common fine wiring plane, said fine wiringplane having a plurality of contact pads configured in said edge regionof said leadframe.
 21. The panel according to claim 20, wherein: saidplurality of leadframe positions are configured in rows and columns. 22.The panel according to claim 21, wherein the panel has a panel memberwith a form and a size corresponding to a semiconductor wafer or to aprinted circuit board.